1. Field of the Invention
The present application relates generally to a design structure and more specifically, to a design structure for a phase locked loop with stabilized dynamic response.
2. Background of the Invention
A phase locked loop (PLL) is a closed loop feedback control system that generates an output signal in relation to the frequency and phase of an input, or reference, signal. The PLL automatically responds to the frequency and phase of the input signal by raising or lowering the frequency of a controlled oscillator until it is matched to the reference in both frequency and phase.
PLLs are widely used in computing devices, telecommunications systems, radio systems, and other electronic applications where it is desired to stabilize a generated signal or to detect signals in the presence of noise. Since an integrated circuit can hold a complete PLL, the use of PLLs in modern electronic devices is widespread.
PLLs generally include a phase detector circuit, a low pass filter circuit, and a voltage controlled oscillator (VCO) placed in a negative feedback configuration. In addition to these elements, a frequency divider circuit may be provided in the feedback path, the reference signal path, or both, in order to make the PLL's output signal an integer multiple of the reference signal. The phase detector compares the phase of two inputs and outputs a corrective signal to control the VCO such that the phase difference between the two inputs becomes zero. The two inputs are a reference signal and the divided output of the VCO.
Various types of phase detector circuits are known including simple OR gates, four-quadrant multiplier (or “mixer”) circuits, proportional phase detector circuits, and the like. A more complex phase detector uses a simple state machine to determine which of the two signals has a zero-crossing earlier or more often. This brings the PLL into lock even when it is off frequency. This type of phase detector circuit is known as a phase frequency detector (PFD).
The VCO is used to generate a periodic output signal. For example, if the VCO is at approximately the same frequency as the reference signal, if the phase of the VCO falls behind the phase of the reference signal, the phase detector circuit causes a charge pump of the PLL to charge the control voltage so that the VCO speeds up. Likewise, if the phase of the VCO progresses ahead of the phase of the reference signal, the phase detector circuit causes the charge pump to change the control voltage to slow down the VCO. The low-pass filter smooths out the abrupt control inputs from the charge pump. Since the frequency of the VCO may be far from the frequency of the reference signal, practical phase detectors may also respond to frequency differences, such as by using a phase frequency detector (PFD), so as to increase the lock-in range of allowable inputs.
As discussed above, most PLLs also include a frequency divider circuit between the VCO and the feedback input to the phase detector circuit in order to produce a frequency synthesizer. This frequency divider circuit may be programmable so as to achieve different output or feedback frequencies of the output signal. Some PLLs may also include a frequency divider circuit between the reference clock input and the reference input to the phase detector circuit. If this frequency divider circuit divides the frequency of the reference signal by M, the inclusion of this frequency divider circuit between the reference clock input and the reference input to the phase detector circuit allows the VCO to multiply the reference signal's frequency by N/M, where N is the multiplier provided by the VCO.
PLLs are used in a number of different ways in modern electronic systems. One use of PLLs is to provide clock signals for processors and other electronic devices. Typically, the clock signals supplied to these processors and other electronic devices come from clock generator PLLs which multiply a lower-frequency reference clock signal up to an operating frequency required by the processor or electronic device. Clock distribution logic may then distribute the clock signal generated by the PLL to various endpoints in the processor or electronic device.
Another use of PLLs is to provide a spread spectrum functionality to reduce interference with other electronic devices by spreading the energy of an input signal over a larger portion of the frequency spectrum of the PLL output. All electronic devices or systems emit some unwanted energy. Various regulatory agencies, such as the Federal Communications Commission (FCC), impose limits on this emitted energy and any interference it may cause on other electronic devices. This emitted interference, or noise, generally appears as sharp spectral peaks, usually at the operating frequency of the device generating the noise, and a few harmonics of this operating frequency. A system designer may use a spread-spectrum PLL to reduce interference with high-Q receivers by spreading the energy over a larger portion of the frequency spectrum of the PLL output. For example, by changing the operating frequency up and down by a small amount, a device running at hundreds of megahertz can spread its interference evenly over a few megahertz of spectrum. This drastically reduces the amount of noise seen by other electronic devices.
The dynamic responsiveness of a PLL is measured primarily with regard to the PLL's damping factor and loop bandwidth. The damping factor is a measure of how responsive the PLL is to changing the phase/frequency of the reference input signal. If a PLL takes too much time to adjust its response to achieve a desired phase/frequency, the PLL is over-damped. If the PLL tends to oscillate towards its desired phase/frequency, then the PLL is under-damped. A PLL that does not overshoot the desired phase/frequency and achieves the desired phase/frequency within a minimum period of time is determined to be critically damped.
The loop bandwidth represents the frequencies of reference signals or input signals that the PLL will detect. The PLL acts as a filter meaning that input signals having a frequency within a specific range will be detected for adjustment by the PLL. Other input signals outside of the range, or bandwidth, will not be detected by the circuitry of the PLL and thus, are essentially filtered-out. Large loop bandwidth PLLs tend to lock onto the reference input signal more quickly than small loop bandwidth PLLs. Small loop bandwidth PLLs take longer to lock, but are able to filter out more noise or jitter.
Phase locked loop (PLL) circuits for applications, such as processor core clock generation, usually require damping factors between 0.5 and 1.0, 1.0 being a critically damped PLL circuit, and loop bandwidths of at least 100 times the spread spectrum modulation frequency for proper spread spectrum tracking with no additional spread spectrum induced jitter penalty, e.g., 50 KHz modulation frequency means 5 MHz minimum PLL bandwidth is required. However, excessive PLL bandwidth will cause larger jitter due to external noise. Thus, it is important to optimize the bandwidth of a PLL circuit so as to obtain as small a PLL bandwidth as possible, while still providing proper spread spectrum tracking. Moreover, it is important to obtain as close to an optimal damping factor as possible with PLL circuits.
While PLLs provide the ability to adjust the phase and frequency of input signals, the dynamic responsiveness of PLLs must be selected carefully to meet the requirements of the system in which they are utilized. Optimization of the dynamic response of PLLs is often very difficult to achieve because the damping factor and natural frequency/loop bandwidth cannot be set independently for conventional PLL designs. That is, in conventional PLL designs, any modification to the damping factor of the PLL will also cause a modification in the loop bandwidth. Similarly, modifications to the loop bandwidth will cause a change in the damping factor of the PLL. It is not currently possible to adjust one dynamic response parameter of a PLL independently of the other.